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SPLC563A
320-Channel Low-Voltage Segment Driver for Dot-Matrix STN Liquid Crystal Display
MAY. 16, 2005 Version 1.0
Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be accurate and reliable. However, Sunplus Technology makes no warranty for any errors which may appear in this document. Contact Sunplus Technology to obtain the latest version of device specifications before placing your order. No responsibility is assumed by Sunplus Technology for any infringement of
patent or other rights of third parties which may result from its use. In addition, Sunplus products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPLC563A
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 3 2. FEATURES .................................................................................................................................................................................................. 3 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3.1. BLOCK FUNCTION DESCRIPTIONS ........................................................................................................................................................... 4 3.1.1. Liquid crystal drive circuit .......................................................................................................................................................... 4 3.1.2. Level shifter............................................................................................................................................................................... 4
3.1.3. Latch circuit 2 ............................................................................................................................................................................ 4 3.1.4. Latch circuit 1 ............................................................................................................................................................................ 4 3.1.5. Shift register.............................................................................................................................................................................. 4 3.1.6. Data rearrangement circuit ....................................................................................................................................................... 4 3.1.7. Timing generator circuit............................................................................................................................................................. 4 4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5 5. REARRANGING OUTPUT DATA (SHL)...................................................................................................................................................... 7 6. OPERATION TIMING .................................................................................................................................................................................. 8 6.1. 4-BIT CAPTURE MODE (1LINE, 640 DOTS)............................................................................................................................................... 8 6.2. 8-BIT CAPTURE MODE (1LINE, 640 DOTS)............................................................................................................................................... 9 7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 10 7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 10 7.1.1. Turning on the power ...............................................................................................................................................................11 7.1.2. Turning off the power ...............................................................................................................................................................11 7.2. DC CHARACTERISTICS 1 .......................................................................................................................................................................11 7.3. DC CHARACTERISTICS 2 ...................................................................................................................................................................... 12 7.4. AC CHARACTERISTICS 1 ...................................................................................................................................................................... 13 7.5. AC CHARACTERISTICS 2 ...................................................................................................................................................................... 14 8. APPLICATION CIRCUIT ........................................................................................................................................................................... 16 9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 17 9.1. PAD ASSIGNMENT AND LOCATIONS....................................................................................................................................................... 17 9.2. ORDERING INFORMATION ..................................................................................................................................................................... 17 10. DISCLAIMER............................................................................................................................................................................................. 18 11. REVISION HISTORY ................................................................................................................................................................................. 19
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SPLC563A
320-CHANNEL LOW-VOLTAGE SEGMENT DRIVER FOR DOT-MATRIX STN LIQUID CRYSTAL DISPLAY
1. GENERAL DESCRIPTION
The SPLC563A is a 320-channel segment driver for driving a dot-matrix STN liquid-crystal panel at a low voltage. The driver can also correspond to 240-channel output by switching mode. It operates at a low voltage: a liquid-crystal drive voltage of 5.0V and a logic drive voltage of 3.0V, and is used together with common driver SPLC564A. The package, which adopts a flexible TCP, can be applied to various liquid crystal panels.
2. FEATURES
Display duty: Up to 1/240 Liquid crystal drive voltage: 2.6V to 5.5V Number of liquid crystal drive circuits: 320 circuits Operating voltage: 2.5V to 5.5V Number of data bits: 4 or 8 bits
Shift clock speed: 8.0MHz max @ 5.0V, 6.5MHz max @ 3.0V Together with the common drivers SPLC564A Low power consumption Display-off function Flexible TCP
Switching output mode: 320 output mode, 240 output mode
3. BLOCK DIAGRAM
V0L VML V1L
VCC GND2 GND1 CL1 M BS
D0-D7
SHL MODE
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Standby function
Y0 - Y319 Liquid crystal drive circuit Level shifter Timing generator circuit Latch circuit 2 Latch circuit 1 Latch circuit 1 Data rearrangement circuit Shift register EIO1 EIO2
Automatic generation of chip-enable signals
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* V0L VML V1L
Level shifter DISPOFF
CL2
Note: PINs V0L, VML, and V1L are internally connected to pins V0R, VMR, and V1R, respectively.
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3.1. Block Function Descriptions 3.1.1. Liquid crystal drive circuit
Selects and outputs the liquid crystal drive level V0, VM, or V1 by
3.1.5. Shift register
80-bit shift register, which generates data-capture signals for latch circuits 1 at the fall of CL2.
DISPOFF and a combination of data for latch circuit 2 and signal
M.
3.1.6. Data rearrangement circuit
Inverts the order of data output crosswise.
3.1.2. Level shifter
Converts logic signals to liquid crystal drive signals.
3.1.7. Timing generator circuit
The timing generator circuit generates data latch pulses for latch circuit2 and changes pulse the LCD drive outputs to AC.
3.1.3. Latch circuit 2
320-bit latch circuit, which latches the data of latch circuits 1 at the fall of CL1 and outputs the data to the level shifter.
3.1.4. Latch circuit 1
4/8-bit parallel data latch circuit, which latches display data D0 to D7 according to signals transmitted from the shift register.
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4. SIGNAL DESCRIPTIONS
Classification Power supply Symbol VCC GND1 GND2 V0L V0R VML VMR V1L V1R Control signal CL2 M 377 381 Clock 2 M Input Input CL1 PAD No. 347 353 385 342 391 339 394 345 388 379 V0L V0R VML VMR V1L V1R Clock 1 Input Input Liquid crystal drive level power supply
V0 VM
Connected to VCC GND
I/O -
Functions VCC - GND: Power supply for logic.
Latch signal of display data: A liquid crystal drive signal corresponding to display data is output at the fall of CL1.
Capture signal of display data: Display data is captured at the fall of CL2. A.C. signal of liquid crystal drive output
Display data Liquid crystal drive output Selected level
DISPOFF
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D0 to D7 361, 369 363, 371 365, 373 367, 375 355 357 DATA0 to DATA7 Input
1 (VCC level) 0 (GND level) Not-selected level
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Liquid crystal drive output ON OFF
SHL
Shift Left
Input I/O
Control signal for inverting the order of data output (see the following page)
SHL
EIO1
Enable IO1
GND VCC
Enable input
Enable Output Enable input
Enable output
EIO2
383
Enable IO2
I/O
Enable input: The enable input of the first IC is connected to the GND and another is connected to the enable output of the second IC. Enable output: Connected to the enable input of the second IC at cascade output. Grounding DISPOFF sets liquid crystal drive output Y0 - Y319 to the VM level.
359
Disp off
Input
BS
351
Bus Select
Input
Switches the number of input bits for the display data.
VCC 8-bit input mode
GND
4-bit input mode (Captures data from D0 - D3. At this time, connect D4 - D7 to the GND.)
MODE
349
MODE
Input
Switches the number of input bits for the display data.
VCC GND 320 output mode 240 output mode (Y40 - Y279 are valid output. The other 80 pins output the not-selected-level signals synchronized every time; release these pins.)
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Classification Liquid crystal drive output Symbol Y0 to Y319 PAD No. 328 to 9 Connected to Y0 to Y319 I/O Output Functions Liquid crystal drive output: Selects and outputs level V0 or V1 according to the combination of the M signal and display data when DISPOFF is connected to VCC.
M 1 0
D O u tp u t le v e l
1
0
1
0
V0
V1
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5. REARRANGING OUTPUT DATA (SHL)
SHL = GND, BS = GND Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y312 Y314 Y316 Y318 Y313 Y315 Y317 Y319 D3 D2 D1 D0 D3 D2 D1 D0 Last data Enable input: EIO1 Enable output: EIO2 SHL = VCC, BS = GND Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
D3 D2 D1 D0 D3 D2 D1 D0 First data
D0 D1 D2 D3 D0 D1 D2 D3 Last data
SHL=GND, BS = VCC Y0 Y1 Y2 Y3
D7 D6 D5 D4 D3 D2 D1 D0 First data
SHL = VCC, BS = VCC Y1 Y2 Y3 Y4
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Enable input: EIO2 Enable output: EIO1 Y4 Y5 Y6 Y7 Enable input: EIO1 Enable output: EIO2 Y5 Y6 Y7 Y8 Last data Enable input: EIO2 Enable output: EIO1
Y312 Y314 Y316 Y318 Y313 Y315 Y317 Y319 D3 D2 D1 D0 D3 D2 D1 D0 First data
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Y312 Y314 Y316 Y318 Y313 Y315 Y317 Y319 D7 D6 D5 D4 D3 D2 D1 D0 Last data
Y315 Y317 Y319 Y313 Y314 Y316 Y318 Y320 D0 D1 D2 D3 D4 D5 D6 D7 First data
D0 D1 D2 D3 D4 D5 D6 D7
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6. OPERATION TIMING
6.1. 4-Bit Capture Mode (1line, 640 dots)
Line
CL2 1 2 79 80 81 82 159 160 161
D0 to D3
d4
d8
d316
d320
d1
d5
d313
d317
CL1
EIO2 (No.1)
EIO2 (No. 2)
Y0 - Y319
BS = GND (4-bit capture mode)
During the data standby state when the data capture operation
enable signal is low (SHL = GND: EIO1 ), the next data capture clock (CL2) cancels the standby state. The 4-bit data is captured
at the fall of CL2. When 316 bits are captured, the enable signal becomes the GND level (SHL = GND: EIO2 ). When 320 bits
are captured, the operation automatically stops (the standby state is entered).
The second IC is then activated when pin EIO2 is
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Data capture period for IC (No. 1) Data capture period for IC (No. 2)
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connected to pin EIO1 of the second IC.
Data output changes at the fall of CL1.
During SHL = GND, captured data d1 and d320 are output to Y0 During SHL = VCC, data d1 and d320
and Y319, respectively.
are output to Y319 and Y0, respectively.
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6.2. 8-Bit Capture Mode (1line, 640 dots)
Line
CL2 1 2 39 40 41 42 79 80
D0 to D7
d8
d16
d312
d320
d1
d9
d305
d313
CL1
EIO2 (No.1)
EIO2 (No. 2)
Y0 - Y319
BS = VCC (8-bit capture mode)
The 8-bit display data is captured at the fall of CL2.
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Data capture period for IC (No. 1) Data capture period for IC (No. 2)
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Other basic operations are the same as those of the 4-bit capture mode.
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7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Item Power supply voltage for logic circuits Power supply voltage for LCD drive circuits Input voltage 1 Input voltage 2 Operating temperature Storage temperature
Note1: Potential from the GND Note2: Applied to pins SHL, EIO1 , EIO2 , DISPOFF , D0 to D7, CL1, CL2, M, BS, and MODE. Note3: Applied to VML, VMR, V1L, and VMR. in normal operation. Exceeding the conditions will cause malfunctions or will affect LSI reliability.
Symbol VCC V0 VT1 VT2 TOPR TSTG
Rating -0.3 to + 7.0 -0.3 to + 7.0 -0.3 to VCC + 0.3 -0.3 to V0 + 0.3 -30 to +75 -55 to +110
Unit V V V V C
Notes 1, 4 1, 4 1, 2 1, 3, 4
Operating the LSI in excess of the absolute maximum rating will result in permanent damage. Use the LSI observing electrical characteristic conditions Note4: Conform to the following turn-on/off sequence of the power and signals. addition, LSI reliability will be affected.
VCC
V0
VM V1
DISPOFF
Input-signal clock data
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2.7V 0ms VM V1 0ms 0ms 0ms 0ms Signal-undefined period Initialization period (at leat one frame)
Otherwise, the LSI will malfunction or will be permanently damaged.
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In
2.7V
0ms
(0 ms: Minimum value)
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7.1.1. Turning on the power
1). Turn on the power in the order of GND- VCC, GND-V0, and VM/V1. Then, ground the DISPOFF pin. 2). The LCD forcibly outputs the VM level by the DISPOFF function. 3). Even if an input signal is disturbed immediately after VCC is applied, the DISPOFF function has priority. 4). Input the specific signal to initialize registers in the driver. The initialization period must be at least one frame. 5). The preparation of normal display is completed. Input the
VCC level
to the DISPOFF pin to cancel the
DISPOFF function. At this time, the level of pins V0, VM, and V1 must rise to the specific potential.
7.1.2. Turning off the power
The procedure is basically the reverse for turning on the power. 1). Ground the DISPOFF pin. 2). Turn off the liquid crystal power in the order of VM/V1 and GND-V0. 3). Ground VCC and an input signal.
At this time, the level of pins V0, VM, and V1 must fall to 0 V. Since the DISPOFF function stops when output a level other than VM. Therefore, a display failure may occur when the power is turned off or on.
7.2. DC Characteristics 1
Item
Input high voltage
Input low voltage
Output high voltage Output low voltage
Vi-Yj on resistance
Input leakage current 1
Input leakage current 2 Current consumption 1 Current consumption 2 Current consumption
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Symbol VIH Pins Min. Typ. Max. VCC Unit V CL1, CL2, SHL, M, 0.8 x VCC
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VCC falls
to 0 V, the LCD may
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Notes
(VCC = 2.5 to 4.5V, V0 - GND = 2.6V to 5.5V, TA = -30C to +75C) Test Condition
EIO1 , EIO2
VIL
MODE, DISPOFF ,
0
-
0.2 x VCC
D0 to D7, BS
VOH VOL
EIO1 , EIO2 EIO1 , EIO2
VCC - 0.4 -
-
-
V
IOH = -0.4mA IOL = 0.4mA 1
-
0.4
V
RON
Y0 to Y319, V0L, R
0.7
2.0
K
ION = 150A
Y0 to Y319, VML, R Y0 to Y319, V1L, R
-
2.0
3.0
K A
-
0.7 -
2.0
K
IIL1
CL1, CL2, SHL, M,
-5.0
5.0
VIN = VCC to GND
EIO1 , EIO2 ,
MODE, DISPOFF ,
D0 to D7, BS
IIL2
VML, R, V1L, R VCC
-25 -
-
25
A
VIN = V0 to GND 2
ICC IV0 IST
150 60 50
300
A
VCC = 3.3V V0 = 2.7V fCL2 = 3.5MHz
V0L, R VCC
-
200 100
A
fCL1 = 19.2KHz A fM = 1.5KHz 2,3
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7.3. DC Characteristics 2
(VCC = 4.5 to 5.5V, V0 - GND = 2.6V to 5.5V, TA = -30C to +75C) Item Input high voltage Symbol VIH Pins CL1, CL2, SHL, M, Min. 0.8 x VCC Typ. Max. VCC Unit V Test Condition Notes
EIO1 , EIO2
Input low voltage VIL MODE, DISPOFF , D0 to D7, BS Output high voltage Output low voltage Vi-Yj on resistance VOH VOL RON 0 0.2 x VCC V
EIO1 , EIO2 EIO1 , EIO2
Y0 to Y319, V0L, R Y0 to Y319, VML, R Y0 to Y319, V1L, R
VCC - 0.4 -5.0
0.7 2.0 0.7 -
0.4 2.0 3.0 2.0 5.0
V V K K
IOH = -0.4mA IOL = 0.4mA
Input leakage current 1
IIL1
CL1, CL2, SHL, M,
Input leakage current 2 Current consumption 1 Current consumption 2 Current consumption
V0 - GND = 5.5V V1 = GND + 1.0
Note1: Resistance between pins Y and V when a load current flows to one of the pins from Y0 to Y319. VM = (V0 + V1)/2
The voltage range of the liquid crystal drive level power supply is described. A voltage around the GND is applied to pin V1, and an intermediate voltage of about V0 and V1 is applied to pin VM. Use the V1 in the range of DV = 0.25 x V0, in which the impedance Ron of driver output is stable.
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MODE, DISPOFF , D0 to D7, BS IIL2 VML, R, V1L, R VCC -25 25 A ICC IV0 230 60 450 A V0L, R VCC 200 A IST 80 150 A
EIO1 , EIO2 ,
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VIN = VCC to GND
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1 2 2,3
VIN = V0 to GND
VCC = 5.0V V0 = 2.7V fCL2 = 3.5MHz
fCL1 = 19.2KHz fM = 1.5KHz
The following conditions are defined:
V0
VM
V = 0.25 x V0
V1 GND
Relationship between the driver output waveform and each level voltage. Note2: A current flowing in the input or output section is excluded. If an input signal is at an intermediate level for the CMOS, a through-current flows in the input circuit and power supply current increases. Therefore, VIH must be at the VCC level and VIL must be at the GND level. Note3: Current at standby Note4: The voltage of each signal is shown below.
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Segment Voltage Segment wavform Common wavform Common Voltage VH (23.0V)
V0 (5.0V)
VCC (3.3V) VM (3.0V)
V1 (1.0V) GND (0.0V)
7.4. AC Characteristics 1
Item
Clock cycle time
Clock high pulse width 1 Clock low pulse width 1
Clock high pulse width 2 Clock setup time Clock hold time Clock rise time Clock fall time
Data setup time Data hold time M setup time M hold time
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Normal display period Display-off period Normal display period Display-off period
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GND (0.0V)
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VL (-17.0V)
(VCC = 2.5V to 4.5V, V0 - GND = 2.6V to 5.5V, TA = -30C to +75C) Min. 152 65 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tCYC
Pins CL2
tCWH2 tCWL2
CL2
-
CL2
65
-
tCWH1 tSCL
CL1
65
-
CL1, CL2
80
-
tHCL tr tf
CL1, CL2 CL1, CL2 CL1, CL2
80 -
-
30 30 -
tDS
D0 to D7, CL2 D0 to D7, CL2 M, CL1 M, CL1
50
tDH
50 20 20 -
tMS tMH tpd1
1000
Output delay time 1
CL1, Y0 to Y319
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7.5. AC Characteristics 2
(VCC = 4.5V to 5.5V, V0 - GND = 2.6V to 5.5V, TA = -30C to +75C) Item Clock cycle time Clock high pulse width 1 Clock low pulse width 1 Clock high pulse width 2 Clock setup time Clock hold time Clock rise time Clock fall time Data setup time Data hold time M setup time M hold time Symbol tCYC tCWH2 tCWL2 tCWH1 tSCL tHCL t4 tf tDS tDH tMS Pins CL2 CL2 CL2 CL1 CL1, CL2 CL1, CL2 CL1, CL2 CL1, CL2 D0 to D7, CL2 D0 to D7, CL2 M, CL1 Min. 125 45 45 45 80 80 20 20 Max. Unit ns ns ns ns ns ns
Output delay time 1
Note1: A load must be 10pF or less for EI/O connection between drivers.
Note2: For output delay time 1 and 2, connect the load circuit shown below.
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tMH M, CL1 20 tpd1 CL1, Y0 to Y319 1000
20
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ns ns ns ns ns ns ns
Test Point
100pF
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tr tCWH2 0.8 VCC tf tCWH2 tCYC
CL2
0.2 VCC tDS 0.8 VCC tDH
D0 - 7
0.2 VCC
tCWH1 0.8 VCC
CL1
CL2
M
CL1
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0.2 VCC tSCL tHCL 0.2 VCC tMS tMH 0.8 VCC 0.2 VCC 0.2 VCC tpd1 0.8 V0 0.2 V1
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8. APPLICATION CIRCUIT
VLL, R VML, R VHL, R VLCDL, R VEEL, R DIO1 DISPOFF SHL MWS4 - 0 M GND CL VCC MODE COM237 COM238
SEG1 SEG2 SEG3 X240 TO X1 SPLC564A
COM1 COM2 COM3 COM4
LCD Panel 640 X 240 1/240 duty
VLCD VH(COM) VCC VM V0(SEG) V1(SEG) GND VEE
Power supply circuit
COM239 COM240
Controller
Note1: When designing the board, connect a capacitor near the IC to stabilize power supply. Use two capacitors of about 0.1F for each IC (between VCC and GND, V0 and GND, VLCD and GND, and VEE and GND). Note2: In addition, for the power supply circuit, connect a capacitor of several F or several tens of F between the liquid crystal power supply and GND. For set evaluation, confirm that there is no inversion of liquid crystal drive power supply and level power supply in the period between when the liquid crystal drive power supply is turned on and when it is turned off. Note3: Configuring the LCD panel using the SPLC563A when using the select COMMON driver.
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SPLC563A
DISPOFF DISPOFF GND1, 2 GND1, 2 VML, R V1L, R V0L, R MODE D0 - 7 D0 - 7 EIO1 EIO2 EIO2 VCC EIO1
Y319 TO Y0
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SEG637
SEG638
SEG639
SEG4
Y319 TO Y0
SPLC563A
O
MODE VCC BS
V1L, R
CL1
D0 - 7
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DISPOF
FLM
CL2
M
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V0L, R
VL(COM)
VML, R
SHL
SHL
CL1
CL2
BS
M
SEG640
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SPLC563A
9. PACKAGE/PAD LOCATIONS
9.1. PAD Assignment and Locations
Please contact Sunplus sales representatives for more information.
9.2. Ordering Information
Product Number SPLC563A-C SPLC563A-PT122 Package Type Chip form Package form - TCP 4SP, 70W
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10. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. Please note that application circuits
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only.
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11. REVISION HISTORY
Date MAY. 16, 2005 Revision # 1.0 Description 1. Correct PIN No. in section "4. SIGNAL DESCRIPTIONS" 2. Delete Pin Map 3. Correct VCC connection in "8. APPLICATION CIRCUIT" JUN. 13, 2003 JUL. 12, 2001 0.2 0.1 Modify "9. PACKAGE/PAD LOCATIONS" Original Page 5-6 6 16 17
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MAY. 16, 2005 Version: 1.0

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